The present invention relates to an impedance matching circuit used in various semiconductor integrated circuits such as a semiconductor memory device, and more particularly to a calibration circuit configured to more easily correct an error occurring in the impedance matching circuit.
Semiconductor devices implemented by integrated circuit (IC) chips such as central processing units (CPUs), memories, and gate arrays are incorporated into a variety of electrical products such as personal computers, servers and workstations. Most of semiconductor devices include an input circuit configured to receive signals from the outside via input pads and an output circuit configured to provide internal signals to the outside via output pads.
As the operating speed of electrical products is increasing, a swing width of a signal exchanged between semiconductor devices is being gradually reduced for minimizing a delay time taken for signal transmission. However, as the swing width of the signal is being reduced, an external noise has a greater influence on the signal transmission and signal reflection becomes more critical at an interface terminal due to impedance mismatch. Such impedance mismatch is generally caused by an external noise, a variation of a power supply voltage, a change in an operating temperature, a change in a manufacturing process, etc. The impedance mismatch may lead to a difficulty in high-speed transmission of data and distortion in output data. Therefore, if semiconductor devices receive the distorted output data through an input terminal, it frequently gives rise to problems such as a setup/hold failure and an error in decision of an input level.
In particular, in order to resolve the above problems, a memory device requiring high-speed performance employs an impedance matching circuit near around a pad inside an IC chip. In order to match the impedance between devices, typically source termination is performed at a transmitting end by an output circuit, and parallel termination is performed at a receiving end by a termination circuit connected in parallel to an input circuit.
ZQ calibration refers to a procedure of generating pull-up and pull-down codes which are varied with PVT (process, voltage and temperature) conditions. The resistance of the input and output circuits, e.g., a termination resistance at a DQ pad in a semiconductor memory device, is calibrated using the codes resulting from the ZQ calibration. Here, the term of ZQ calibration is attributed to the fact that the calibration is performed using a ZQ node.
Hereinafter, how the ZQ calibration is performed in a calibration circuit will be described.
FIG. 1 is a block diagram of a conventional calibration circuit for performing ZQ calibration.
Referring to FIG. 1, the conventional calibration circuit configured to perform ZQ calibration includes a first calibration resistor unit 110, a dummy calibration resistor unit 120, and a second calibration resistor unit 130, a reference voltage generator 102, comparators 102 and 103, and counters 105 and 106. The first calibration resistor unit 110 is provided with a plurality of pull-up resistors that are turned on/off in response to a pull-up calibration code PCODE<0:N>. The dummy calibration resistor unit 120 has the same construction as the first calibration resistor unit 110. The pull-down calibration resistor unit 130 is provided with a plurality of pull-down resistors that are turned on/off in response to a pull-down calibration code NCODE<0:N>.
The first calibration resistor unit 110 is calibrated to an external resistor 101 connected to a ZQ node to generate the calibration code PCODE<0:N>. The second calibration resistor unit 130 is calibrated to a dummy calibration resistor unit 120 to generates the calibration code NCODE<0:N>, wherein the dummy calibration resistor unit 120 has the same resistance as the first calibration resistor unit 110 using the calibration code PCODE<0:N>.
As for the operation, the comparator 103 compares a ZQ node voltage with a reference voltage VREF (generally, set to VDDQ/2) generated from a reference voltage generator 102, thereby generating up/down signals. Herein, the ZQ node voltage is generated by coupling the first calibration resistor unit 110 to an external resistor 101 (generally, 240Ω) connected to a ZQ pin that is coupled to the ZQ node.
The pull-up counter 105 receives the up/down signals to generate the pull-up calibration code PCODE<0:N> as a binary code, which turns on/off the resistors connected in parallel in the first calibration resistor unit 110, thereby calibrating total resistance of the first calibration resistor unit 110. The calibrated resistance of the first calibration resistor unit 110 affects the ZQ node voltage again, and the above-described calibration procedure is then repeated. That is, the first calibration resistor unit 110 is calibrated such that the total resistance of the first calibration resistor unit 110 is equal to the resistance of the external resistor 101, which is called a pull-up calibration.
The binary code, i.e., the pull-up calibration code PCODE<0:N>, generated during the pull-up calibration is inputted into the dummy calibration resistor unit 120 to determine total resistance of the dummy calibration resistor unit 120 which is equal to resistances of the first calibration resistor unit 110 and the external resistor 101. Thereafter, a pull-down calibration starts to be performed in a similar manner to the pull-up calibration. Specifically, the pull-down calibration is performed such that a voltage of a node A is equal to the reference voltage VREF using the comparator 104 and the pull-down counter 106, that is, the total resistance of the second calibration resistor unit 130 is equal to the total resistance of the dummy calibration resistor unit 120.
The binary codes PCODE<0:N> and NCODE<0:N> resulting from the ZQ calibration, i.e., pull-up and pull-down calibrations, are inputted to pull-up and pull-down resistors (termination resistors) at input/output pads, which are identically configured to the pull-up and pull-down calibration resistor units in the calibration circuit of FIG. 1, thus determining termination resistance. In a semiconductor memory device, resistances of pull-up and pull-down resistors at a DQ pad are determined.
For reference, although both pull-up and pull-down calibration operations are performed to generate pull-up calibration codes PCODE<0:N> and pull-down calibration codes NCODE<0:N> for determining resistances of the pull-up and pull-down resistors at input/output pads, both of the pull-up and pull-down resistors are not always provided at the input/output pads. For example, in a semiconductor memory device, both the pull-up and pull-down resistors are used at an output driver but only the pull-up resistor is used at an input buffer.
Therefore, if only the pull-up resistor is provided at input/output pads, the calibration circuit of FIG. 1 only includes the pull-up calibration resistor unit 110, the counter 105 and the comparator 103, which are configured to generate the pull-up calibration codes PCODE<0:N>. An operation of this case is the same as the above-described pull-up calibration.
FIG. 2 is a block diagram illustrating the case where the calibration circuit is applied to a semiconductor memory device. Specifically, FIG. 2 illustrates how termination resistance of an output driver of the semiconductor memory device is determined using the calibration codes PCODE<0:N> and NCODE<0:N> generated from the calibration circuit of FIG. 1.
The output driver configured to output data in the semiconductor memory device includes pre-drivers 210 and 220, and pull-up and pull-down termination resistor units 230 and 240 for outputting data.
The pre-drivers 210 and 220 control the pull-up termination resistor unit 230 and the pull-down termination resistor unit 240, respectively. When outputting high-level data, the pull-up termination resistor unit 230 is turned on so that a data pin DQ goes to ‘HIGH’ state. On the contrary, when outputting low-level data, the pull-down termination resistor unit 240 is turned on so that the data pin DQ goes to ‘LOW’ state. That is, the data pin DQ is pull-up or pull-down terminated to thereby output data of logic high or low level.
At this time, number of resistors in the pull-up and pull-down termination resistors 230 and 240 to be turned on is determined by the pull-up and pull-down calibration codes PCODE<0:N> and NCODE<0:N>. Specifically, which resistor unit is turned on between the pull-up and pull-down termination resistor units 230 and 240 is mainly determined depending on logic level of output data, but which resistor is turned on among the resistors provided in one of the termination resistor units 230 and 240 that has been selected to be turned on is determined by the pull-up calibration code PCODE<0:N> or pull-down calibration code NCODE<0:N>.
For reference, target resistances of the pull-up and pull-down termination resistor units 230 and 240 are not necessarily equal to resistances (240Ω) of the calibration resistor units (see 110, 120 and 130 of FIG. 1) but may be a resistance of one-half (120Ω) or one-quarter (60Ω) of 240Ω, etc. In FIG. 2, reference symbols DQP_CTRL and DQN_CTRL inputted to the pre-drivers 210 and 220 denote various control signals exemplarily.
The ZQ calibration operation of the conventional calibration circuit is based on the assumption that there is no mismatch between the resistors of the calibration resistor units (110, 120 and 130 of FIG. 1) and those of the termination resistor units 230 and 240 and the resistance can be increased or decreased at a predetermined ratio.
However, mismatch exists between the resistors due to process variation or the like. Hence, the termination resistor units may not have a target resistance due to a variety of factors such as offset of a comparator in the calibration circuit, a noise in power supply voltage, a line loading, pad resistance and package resistance. If the termination resistor unit does not have a target resistance, there may occur distortion in input/output data. Accordingly, it is necessary to develop a calibration circuit capable of correcting an error.